New virtually scaling free adaptive CORDIC rotator

In this article we propose a novel CORDIC rotator algorithm that eliminates the problems of scale factor compensation and limited range of convergence associated with the classical CORDIC algorithm. In our scheme, depending on the target angle or the initial coordinate of the vector, a scaling by 1 or 1/?2 is needed that can be realised with minimal hardware. The proposed CORDIC rotator adaptively selects appropriate iteration steps and converges to the final result by executing 50% less number of iterations on an average compared to that required for the classical CORDIC. Unlike classical CORDIC, the final value of the scale factor is completely independent of number of executed iterations. Based on the proposed algorithm, a 16-bit pipelined CORDIC rotator implementation has been described. The silicon area of the fabricated pipelined CORDIC rotator core is 2.73 mm2. This is equivalent to 38 k inverter gates in IHP in-house 0.25 ?m BiCMOS technology. The average dynamic power consumption of the fabricated CORDIC rotator is 17 mW @ 2.5 V supply and 20Msps throughput. Currently, this CORDIC rotator is used as a part of the baseband processor for a project that aims to design a single-chip wireless modem compliant with IEEE 802.11a and Hiperlan/2

A CORDIC like processor for computation of arctangent and absolute magnitude of a vector

In this paper, we propose a CORDIC like algorithm for computing absolute magnitude of a vector and its corresponding phase angle. It eliminates scale factor compensation step as well as the addition/subtraction operation along the z datapath. The synthesis result shows that the proposed processor is hardware economic and suitable for low power applications

Baseband processor for IEEE 802.11a standard with embedded BIST

In this paper results of an IEEE 802.11a compliant low-power baseband processor implementation are presented. The detailed structure of the baseband processor and its constituent blocks is given. A design for testability strategy based on Built-In Self-Test (BIST) is proposed. Finally implementational results and power estimation are reported

A 16-bit CORDIC rotator for high-performance wireless LAN

In this paper we propose a novel 16-bit low power CORDIC rotator that is used for high-speed wireless LAN. The algorithm converges to the final target angle by adaptively selecting appropriate iteration steps while keeping the scale factor virtually constant. The VLSI architecture of the proposed design eliminates the entire arithmetic hardware in the angle approximation datapath and reduces the number of iterations by 50% on an average. The cell area of the processor is 0.7 mm2 and it dissipates 7 mW power at 20 MHz frequency

OFDM synchronizer implementation for an IEEE 802.11(a) compliant modem

In OFDM transmissions, synchronization arises to be one of the most critical operations. The reason for that is the preservation of orthogonality: timing offsets and frequency offsets destroy easily this orthogonality, leading to Inter-Symbol Interference (ISI) as well as Inter-Carrier Interference (ICI). This paper is focused on the implementation of a synchronizer for the IEEE 802.11a standard, which is based on the OFDM transmission scheme. Furthermore, during this year the first chips compliant with the standard are to be deployed, for that reason we also present a comparison of our solution, which is based on the one presented in with two other ones proposed

Implementation of an IEEE 802.11a compliant low-power baseband processor

Abstract – In this paper results of an IEEE 802.11a compliant low-power baseband processor implementation are presented. The detailed structure of the baseband processor and its constituent blocks is given. Additionally, the design flow is briefly described and synthesis and layout results are reported

Base band processor for IEEE 802.11a standard with embedded BIST

In this paper results of an IEEE 802.11a compliant low-power baseband processor implementation are presented. The detailed structure of the baseband processor and its constituent blocks is given. A design for testability strategy based on Built-In Self-Test (BIST) is proposed. Finally implementational results and power estimation are reported

Flipping Laboratory Sessions in a Computer Science Course: An Experience Report

Contribution: This article presents an experience report on the application of flipped classroom (FC) to the laboratory sessions (henceforth lab sessions) of an undergraduate computer science course. Background: Hands-on work in computer science lab sessions is typically preceded by technical instructions on how to install, configure, and use the software and hardware tools needed during the lab. In the course under study, this initial explanation took between 14% and 50% of the lab time, reducing drastically the time available for actual practice. It was also observed that students missing any of the labs had trouble catching up. Intended Outcomes: The application of FC is expected to increase the time for hands-on activities, and improve students' performance and motivation. This improvement is expected to be more noticeable in those students who are unable to attend all lab sessions. Application Design: The study compares the application of FC and a traditional methodology. It encompasses two academic courses and involves 434 students and six lecturers. Findings: The FC is suitable for lab sessions in computer science. Among other results, flipping the labs resulted in 24 more minutes of practical and collaborative work on average at each lab session. It was observed a significant improvement in the motivation of students, with 9 out of every 10 students preferring it over traditional methodologies. Also, the FC made it much easier for students to catch up after missing a lab, making the final grades less dependent on lab attendance

Flipping Laboratory Sessions: An Experience in Computer Science

This paper reports our experience in flipping a second- year undergraduate course on software architecture and integration, taught in the second course of a Software Engineering degree. We compare the application of the flipped-classroom methodology with a traditional methodology. Our study encompasses two academic courses, in the years 2017 and 2018, and involves a total number of 434 students and 6 lecturers, placing this among the largest studies on flipped-classroom to date. The paper also reports on the production of the videos used with the flipped-classroom methodology, recorded by the lecturers in informal settings, and provides several lessons learned in this regard. The results of the study, backed by a solid statistical analysis of the data, demonstrate the suitability of the flipped-classroom methodology for laboratory sessions in the subject course. Among other results, our analysis concluded that students had on average 24 more minutes per session to solve in-class exercises with the flipped-classroom methodology; more than 70% of the students considered that the quantity, duration and didactic content of the videos were (very) appropriate; and 9 out of every 10 students would prefer this methodology in the laboratory sessions of future courses rather than a traditional face-to-face approach.Junta de Andalucía APOLO (US-1264651)Ministerio de Ciencia, Innovación y Universidades OPHELIA (RTI2018–101204–B–C22)Ministerio de Ciencia, Innovación y Universidades Horatio RTI2018-101204-B-C21Junta de Andalucía EKIPMENT-PLUS (P18-FR-2895